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2026 HPCA: The Last-Level Branch Predictor Revisited

Created2026-03-19|cpubpu

2026 HPCA 论文阅读：The Last-Level Branch Predictor Revisited

2024 MICRO: The Last-Level Branch Predictor

Created2026-03-19|cpubpu

2024 MICRO 论文阅读：The Last-Level Branch Predictor

RISC-V Matrix: PULP Quadrilatero

Created2026-03-13|cpumatrixriscv

RISC-V Matrix 自定义扩展（AME）：PULP Quadrilatero

Ventana Patent(US12487830B1): Prediction unit with first predictor that provides a hashed fetch address of a current fetch block to its own input and to a second predictor that uses it to predict the fetch address of a next fetch block

Created2026-03-10|cpubpubtb

Ventana 专利简介：BTB 预测 ICache Set/Way + SCP 前端完整流水线

Intel Patent(US12190114B2): Segmented branch target buffer based on branch instruction type

Created2026-03-08|cpubpubtb

Intel 专利简介：新型 BTB 结构设计 Segmented BTB

Tenstorrent Patent(US20250328350A1): Branch Status Table and Control Instruction Buffer for Processor Instruction Pipeline

Created2026-03-06|cpubpurestore

Tenstorrent 专利解读: 分支预测恢复时对于控制类指令（如 vsetvl）的处理

Alibaba Patents(US11467844B2): Storing multiple instructions in a single reordering buffer entry

Created2026-03-04|cpuooorob

Alibaba 专利解读: ROB Entry 存储多个指令

SiFive Patents(US20230367715A1): Load-Store Pipeline Selection for Vector

Created2026-03-03|cpuvectorrvv

SiFive 专利解读: Vector Store 旁路 L1D Cache 的预测

SiFive Patents(US20230367599A1): Vector Gather with a Narrow Datapath

Created2026-03-01|cpuvectorrvv

SiFive 专利解读: RVV Gather 操作

Gem5 BDP 实现分析

Created2026-02-23|cpusimulatorgem5bpu

Gem5 Branch Direction Predictor Overview