Tenstorrent Patent(US20250328350A1): Branch Status Table and Control Instruction Buffer for Processor Instruction Pipeline
Tenstorrent 专利解读: 分支预测恢复时对于控制类指令（如 vsetvl）的处理
Alibaba Patents(US11467844B2): Storing multiple instructions in a single reordering buffer entry
Alibaba 专利解读: ROB Entry 存储多个指令
SiFive Patents(US20230367715A1): Load-Store Pipeline Selection for Vector
SiFive 专利解读: Vector Store 旁路 L1D Cache 的预测
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SiFive 专利解读: RVV Gather 操作
gem5 MultiCore Memory System
gem5 多核互联拓扑: Classic 与 Ruby
Gem5 BDP 实现分析
Gem5 Branch Direction Predictor Overview
Gem5 BTB
Gem5 Branch Target Buffer Overview
BTB Overview
Branch Target Buffer(BTB) Design
ICache Prefetcher
l1i cache 硬件预取器简介
Address-Correlating Prefetchers
地址关联数据预取器介绍